tixiv
14 years ago
9 changed files with 475 additions and 4 deletions
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#include "../config.h" |
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#include "../makros.h" |
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#include <avr/interrupt.h> |
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#include <avr/io.h> |
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#include <avr/wdt.h> |
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#include "borg_hw.h" |
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/*
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// Diese #defines werden nun durch menuconfig gesetzt
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// 16 Spalten insgesamt direkt gesteuert, dafür 2 Ports
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#define COLPORT1 PORTC |
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#define COLDDR1 DDRC |
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#define COLPORT2 PORTA |
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#define COLDDR2 DDRA |
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// Der andere Port übernimmt die Steuerung der Schieberegister
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#define ROWPORT PORTD |
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#define ROWDDR DDRD |
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// Clock und reset gehen gemeinsam an beide Schieberegister
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// der reset pin ist negiert
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#define PIN_MCLR PD4 |
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#define PIN_CLK PD6 |
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//das dier sind die individuellen Dateneingänge für die Schieberegister
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#define PIN_DATA PD7 |
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*/ |
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#define COLDDR1 DDR(COLPORT1) |
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#define COLDDR2 DDR(COLPORT2) |
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#define ROWDDR DDR(ROWPORT) |
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#ifdef __AVR_ATmega644P__ |
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/* more ifdef magic :-( */ |
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#define OCR0 OCR0A |
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#define SIG_OUTPUT_COMPARE0 SIG_OUTPUT_COMPARE0A |
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#endif |
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//Der Puffer, in dem das aktuelle Bild gespeichert wird
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES]; |
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//Dieser Interrupt wird je nach Ebene mit 50kHz 31,25kHz oder 12,5kHz ausgeführt
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SIGNAL(SIG_OUTPUT_COMPARE0) |
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{ |
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//Watchdog zurücksetzen
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wdt_reset(); |
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COLPORT1 = (pixmap[0][0][0] & 0x0f) | (pixmap[0][1][0] << 4); |
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COLPORT2 = (pixmap[0][2][0] & 0x0f) | (pixmap[0][3][0] << 4); |
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} |
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void timer0_off(){ |
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cli(); |
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COLPORT1 = 0; |
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COLPORT2 = 0; |
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ROWPORT = 0; |
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#ifdef __AVR_ATmega644P__ |
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TCCR0A = 0x00; |
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TCCR0B = 0x00; |
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#else |
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TCCR0 = 0x00; |
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#endif |
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sei(); |
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} |
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// Den Timer, der denn Interrupt auslöst, initialisieren
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void timer0_on(){ |
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/* TCCR0: FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00
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CS02 CS01 CS00 |
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0 0 0 stop |
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0 0 1 clk |
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0 1 0 clk/8 |
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0 1 1 clk/64 |
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1 0 0 clk/256 |
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1 0 1 clk/1024 |
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*/ |
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#ifdef __AVR_ATmega644P__ |
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TCCR0A = 0x02; // CTC Mode
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TCCR0B = 0x04; // clk/256
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TCNT0 = 0; // reset timer
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OCR0 = 20; // Compare with this value
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TIMSK0 = 0x02; // Compare match Interrupt on
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#else |
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TCCR0 = 0x0C; // CTC Mode, clk/256
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TCNT0 = 0; // reset timer
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OCR0 = 20; // Compare with this value
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TIMSK = 0x02; // Compare match Interrupt on
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#endif |
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} |
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void borg_hw_init(){ |
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//Spalten Ports auf Ausgang
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COLDDR1 = 0xFF; |
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COLDDR2 = 0xFF; |
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//Pins am Zeilenport auf Ausgang
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ROWDDR = (1<<PIN_MCLR) | (1<<PIN_CLK) | (1<< PIN_DATA); |
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//Alle Spalten erstmal aus
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COLPORT1 = 0; |
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COLPORT2 = 0; |
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//Schieberegister für Zeilen zurücksetzen
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ROWPORT = 0; |
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//Alle Zeilen ausgänge an bei gigaborg
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ROWPORT |= (1<<PIN_DATA) | (1<<PIN_MCLR); |
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uint8_t x; |
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for(x=0;x<16;x++){ |
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ROWPORT|= (1<<PIN_CLK); |
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ROWPORT&= ~(1<<PIN_CLK); |
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} |
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timer0_on(); |
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//Watchdog Timer aktivieren
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wdt_reset(); |
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wdt_enable(0x00); // 17ms Watchdog
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} |
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#include "../config.h" |
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#include "../makros.h" |
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#include "../ioport.h" |
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#include <avr/interrupt.h> |
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#include <avr/io.h> |
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#include <avr/wdt.h> |
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#include "borg_hw.h" |
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//Der Puffer, in dem das aktuelle Bild gespeichert wird
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES]; |
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//Eine Zeile anzeigen
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inline void rowshow(unsigned char row){ |
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//die Daten für die aktuelle Zeile auf die Spaltentreiber ausgeben
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COLPORT1 = pixmap[0][row][0]; |
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COLPORT2 = pixmap[0][row][1]; |
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OUTPUT_ON(LATCH_R); |
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OUTPUT_OFF(LATCH_R); |
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COLPORT1 = pixmap[1][row][0]; |
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COLPORT2 = pixmap[1][row][1]; |
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OUTPUT_ON(LATCH_G); |
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OUTPUT_OFF(LATCH_G); |
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COLPORT1 = pixmap[2][row][0]; |
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COLPORT2 = pixmap[2][row][1]; |
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OUTPUT_ON(LATCH_B); |
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OUTPUT_OFF(LATCH_B); |
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} |
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uint32_t mod = 1280000ul; |
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uint32_t akku; |
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unsigned char row = 0; |
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ISR(SIG_OUTPUT_COMPARE0) |
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{ |
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//Watchdog zurücksetzen
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wdt_reset(); |
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akku += mod; |
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OCR1A = akku / 256; |
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rowshow(row); |
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if(++row == NUM_ROWS){ |
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row = NUM_ROWS - 1; |
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} |
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} |
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ISR(INT0_vect){ |
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if(akku > (64ul * 256ul * 64ul)){ |
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akku -= OCR1A - TCNT1; |
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mod = akku / 64; |
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akku = 0; |
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row = 0; |
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OCR1A = 0; |
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TCNT1 = 0xffff; |
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} |
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} |
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void timer0_off(){ |
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cli(); |
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TCCR1B = 0x00; |
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sei(); |
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} |
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// Den Timer, der denn Interrupt auslöst, initialisieren
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void timer1_on(){ |
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TCCR1B = 1; //clk/1
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TIMSK |= (1<<OCIE1A); |
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} |
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void borg_hw_init(){ |
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DDR(COLPORT1) = 0xff; |
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DDR(COLPORT2) = 0xff; |
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SET_DDR(LATCH_R); |
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SET_DDR(LATCH_G); |
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SET_DDR(LATCH_B); |
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timer1_on(); |
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//Watchdog Timer aktivieren
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wdt_reset(); |
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wdt_enable(0x00); // 17ms Watchdog
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} |
@ -0,0 +1,88 @@ |
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mainmenu_option next_comment |
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comment "Borg16 port setup" |
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#define COLPORT1 PORTC |
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#define COLDDR1 DDRC |
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#define COLPORT2 PORTA |
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#define COLDDR2 DDRA |
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#// Der andere Port übernimmt die Steuerung der Schieberegister |
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#define ROWPORT PORTD |
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#define ROWDDR DDRD |
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#// Clock und reset gehen gemeinsam an beide Schieberegister |
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#// der reset pin ist negiert |
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#define PIN_RST PD4 |
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#define PIN_CLK PD6 |
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#//das dier sind die individuellen Dateneingänge für die Schieberegister |
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#define PIN_SHFT1 PD7 |
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choice 'Column Port 1 (right)' \ |
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"PORTA PORTA \ |
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PORTB PORTB \ |
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PORTC PORTC \ |
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PORTD PORTD" \ |
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'PORTC' COLPORT1 |
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choice 'Column Port 2 (left)' \ |
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"PORTA PORTA \ |
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PORTB PORTB \ |
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PORTC PORTC \ |
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PORTD PORTD" \ |
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'PORTA' COLPORT2 |
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choice 'port for row shiftregisters' \ |
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"PORTA PORTA \ |
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PORTB PORTB \ |
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PORTC PORTC \ |
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PORTD PORTD" \ |
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'PORTD' ROWPORT |
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comment "pin numbers on shiftregister port" |
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choice '/MCLR Pin' \ |
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"Pin0 0 \ |
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Pin1 1 \ |
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Pin2 2 \ |
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Pin3 3 \ |
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Pin4 4 \ |
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Pin5 5 \ |
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Pin6 6 \ |
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Pin7 7" \ |
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'Pin4' PIN_MCLR |
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choice 'CLK Pin' \ |
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"Pin0 0 \ |
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Pin1 1 \ |
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Pin2 2 \ |
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Pin3 3 \ |
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Pin4 4 \ |
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Pin5 5 \ |
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Pin6 6 \ |
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Pin7 7" \ |
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'Pin6' PIN_CLK |
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choice 'DATA Pin' \ |
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"Pin0 0 \ |
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Pin1 1 \ |
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Pin2 2 \ |
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Pin3 3 \ |
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Pin4 4 \ |
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Pin5 5 \ |
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Pin6 6 \ |
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Pin7 7" \ |
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'Pin7' PIN_DATA |
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comment "fixing hardwareproblems in software" |
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bool "reverse cols" REVERSE_COLS n |
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bool "invert rows " INVERT_ROWS n |
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comment "for borg jacket" |
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bool "interlaced rows" INTERLACED_ROWS n |
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bool "interlaced cols" INTERLACED_COLS n |
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endmenu |
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mainmenu_option next_comment |
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comment "Rotor port setup" |
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#define COLPORT1 PORTC |
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#define COLDDR1 DDRC |
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#define COLPORT2 PORTA |
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#define COLDDR2 DDRA |
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#// Der andere Port übernimmt die Steuerung der Schieberegister |
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#define ROWPORT PORTD |
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#define ROWDDR DDRD |
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#// Clock und reset gehen gemeinsam an beide Schieberegister |
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#// der reset pin ist negiert |
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#define PIN_RST PD4 |
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#define PIN_CLK PD6 |
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#//das dier sind die individuellen Dateneingänge für die Schieberegister |
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#define PIN_SHFT1 PD7 |
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choice 'Column Port 1 (upper)' \ |
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"PORTA PORTA \ |
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PORTB PORTB \ |
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PORTC PORTC \ |
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PORTD PORTD" \ |
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'PORTC' COLPORT1 |
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choice 'Column Port 2 (lower)' \ |
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"PORTA PORTA \ |
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PORTB PORTB \ |
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PORTC PORTC \ |
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PORTD PORTD" \ |
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'PORTA' COLPORT2 |
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choice 'Latch Red Port' \ |
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"PORTA A \ |
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PORTB B \ |
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PORTC C \ |
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PORTD D" \ |
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'PORTD' LATCH_R_PORT |
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choice 'Latch Red Bit' \ |
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"Pin0 0 \ |
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Pin1 1 \ |
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Pin2 2 \ |
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Pin3 3 \ |
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Pin4 4 \ |
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Pin5 5 \ |
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Pin6 6 \ |
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Pin7 7" \ |
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'Pin0' LATCH_R_BIT |
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choice 'Latch Green Port' \ |
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"PORTA A \ |
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PORTB B \ |
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PORTC C \ |
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PORTD D" \ |
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'PORTD' LATCH_G_PORT |
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choice 'Latch Green Bit' \ |
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"Pin0 0 \ |
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Pin1 1 \ |
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Pin2 2 \ |
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Pin3 3 \ |
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Pin4 4 \ |
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Pin5 5 \ |
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Pin6 6 \ |
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Pin7 7" \ |
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'Pin1' LATCH_G_BIT |
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choice 'Latch Blue Port' \ |
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"PORTA A \ |
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PORTB B \ |
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PORTC C \ |
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PORTD D" \ |
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'PORTD' LATCH_B_PORT |
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choice 'Latch Blue Bit' \ |
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"Pin0 0 \ |
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Pin1 1 \ |
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Pin2 2 \ |
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Pin3 3 \ |
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Pin4 4 \ |
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Pin5 5 \ |
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Pin6 6 \ |
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Pin7 7" \ |
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'Pin2' LATCH_B_BIT |
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endmenu |
@ -0,0 +1,40 @@ |
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// Makros for simplified single pin io access.
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#define PORT_(port) PORT ## port |
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#define DDR_(port) DDR ## port |
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#define PIN_(port) PIN ## port |
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#define PORT(port) PORT_(port) |
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#define DDRR(port) DDR_(port) |
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#define PINN(port) PIN_(port) |
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#define SET_DDR(p) DDRR(p##_PORT) |= (1<<p##_BIT) |
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#define CLEAR_DDR(p) DDRR(p##_PORT) &= ~(1<<p##_BIT) |
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#define OUTPUT_ON(p) PORT(p##_PORT) |= (1<<p##_BIT) |
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#define OUTPUT_OFF(p) PORT(p##_PORT) &= ~(1<<p##_BIT) |
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#define INPUT(p) ((PINN(p##_PORT) & (1<<p##_BIT)) != 0) |
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/*
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Use Like this: |
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#define LED_PORT C |
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#define LED_BIT 7 |
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#define SWITCH_PORT B |
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#define SWITCH_BIT 0 |
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int main(){ |
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SET_DDR(LED); //set to output
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OUTPUT_ON(SWITCH); //turn on pullup
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if(INPUT(SWITCH)){ |
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OUTPUT_ON(LED); |
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}else{ |
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OUTPUT_OFF(LED); |
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} |
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} |
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*/ |
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