From 633c193211da6d5c22483a55e7c197c2734dbb10 Mon Sep 17 00:00:00 2001 From: tixiv Date: Thu, 9 Jul 2009 13:37:11 +0000 Subject: [PATCH] pd1165 support added --- borg_hw/Makefile | 4 + borg_hw/borg_hw_pd1165_test.c | 280 ++++++++++++++++++++++++++++++++++ borg_hw/config.in | 8 +- borg_hw/config_pd1165_test.in | 88 +++++++++++ util.c | 13 +- 5 files changed, 388 insertions(+), 5 deletions(-) create mode 100644 borg_hw/borg_hw_pd1165_test.c create mode 100644 borg_hw/config_pd1165_test.in diff --git a/borg_hw/Makefile b/borg_hw/Makefile index 3b46ee5..f8b74cc 100644 --- a/borg_hw/Makefile +++ b/borg_hw/Makefile @@ -30,6 +30,10 @@ ifeq ($(BORG_HW),HW_PANEL_ONE) SRC = borg_hw_panel_one.c endif +ifeq ($(BORG_HW),HW_PD1165_TEST) + SRC = borg_hw_pd1165_test.c +endif + ifeq ($(SRC),'') $(error no valid hardware driver selected ) endif diff --git a/borg_hw/borg_hw_pd1165_test.c b/borg_hw/borg_hw_pd1165_test.c new file mode 100644 index 0000000..db1964f --- /dev/null +++ b/borg_hw/borg_hw_pd1165_test.c @@ -0,0 +1,280 @@ + +#include "../config.h" +#include "../makros.h" + +#include +#include +#include +#include "borg_hw.h" + +/* +// Diese #defines werden nun durch menuconfig gesetzt + + // 16 Spalten insgesamt direkt gesteuert, dafür 2 Ports +#define COLPORT1 PORTC +#define COLDDR1 DDRC + +#define COLPORT2 PORTA +#define COLDDR2 DDRA + +// Der andere Port übernimmt die Steuerung der Schieberegister +#define ROWPORT PORTD +#define ROWDDR DDRD +// Clock und reset gehen gemeinsam an beide Schieberegister +// der reset pin ist negiert +#define PIN_MCLR PD4 +#define PIN_CLK PD6 +//das dier sind die individuellen Dateneingänge für die Schieberegister +#define PIN_DATA PD7 +*/ + +//#define COLDDR1 DDR(COLPORT1) +//#define COLDDR2 DDR(COLPORT2) +//#define ROWDDR DDR(ROWPORT) + +#define DATAPORT PORTC +#define DATADDR DDR(DATAPORT) + +#define ADDRPORT PORTA +#define ADDRDDR DDR(ADDRPORT) + +#define CTRLPORT PORTD +#define CTRLDDR DDR(CTRLPORT) + +#define BIT_CS0 2 +#define BIT_CS1 3 +#define BIT_CS2 4 +#define BIT_CS3 5 + +#define BIT_RW 6 + +//Der Puffer, in dem das aktuelle Bild gespeichert wird +unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES]; + + + +inline void pd1165_write(uint8_t addr, uint8_t data){ + ADDRPORT = (ADDRPORT & 0xf0) | addr; + + DATAPORT = data; + /* + switch (display){ + case 0: + CTRLPORT &= ~((1<>1) + ((row & 0x01)?8:0 ); + tmp = pixmap[plane][row][0]; + tmp1 = pixmap[plane][row][1]; +#endif +#ifdef REVERSE_COLS + tmp = (tmp >> 4) | (tmp << 4); + tmp = ((tmp & 0xcc) >> 2) | ((tmp & 0x33)<< 2); //0xcc = 11001100, 0x33 = 00110011 + tmp = ((tmp & 0xaa) >> 1) | ((tmp & 0x55)<< 1); //0xaa = 10101010, 0x55 = 1010101 + //COLPORT2 = tmp; + tmp = tmp1; + tmp = (tmp >> 4) | (tmp << 4); + tmp = ((tmp & 0xcc) >> 2) | ((tmp & 0x33) << 2); //0xcc = 11001100, 0x33 = 00110011 + tmp = ((tmp & 0xaa) >> 1) | ((tmp & 0x55) << 1); //0xaa = 10101010, 0x55 = 1010101 + //COLPORT1 = tmp; +#else +#ifdef INTERLACED_COLS + static uint8_t interlace_table[16] = { + 0x00, 0x01, 0x04, 0x05, 0x10, 0x11, 0x14, 0x15, 0x40, 0x41, 0x44, 0x45, 0x50, 0x51, 0x54, 0x55 + }; + //COLPORT1 = interlace_table[tmp&0x0f] | (interlace_table[tmp1&0x0f]<<1); + tmp>>=4; tmp1>>=4; + //COLPORT2 = interlace_table[tmp] | (interlace_table[tmp1]<<1); +#else + //COLPORT1 = tmp; + //COLPORT2 = tmp1; + + pd1165_write(row, tmp); + + +#endif +#endif + +} +*/ + +//Dieser Interrupt wird je nach Ebene mit 50kHz 31,25kHz oder 12,5kHz ausgeführt +SIGNAL(SIG_OUTPUT_COMPARE0) +{ + static unsigned char plane = 0; + unsigned char row = 0; + + //Watchdog zurücksetzen + wdt_reset(); + + for(row=0; row < 8; row++){ + pd1165_write(row, pixmap[plane][row][0]); + CTRLPORT &= ~((1<0;ms--){ #ifdef CAN_SUPPORT @@ -44,7 +49,7 @@ void wait(int ms){ } #endif - while(!(TIFR&0x80)); //wait for compare match flag - TIFR=0x80; //reset flag + while(!(TIFR&(1<