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@ -41,14 +41,26 @@ |
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defined(__AVR_ATmega644P__) || \ |
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defined(__AVR_ATmega1284__) || \ |
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defined(__AVR_ATmega1284P__) |
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/* more ifdef magic :-( */ |
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#define OCR0 OCR0A |
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#define TIMER0_COMP_vect TIMER0_COMPA_vect |
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# define TIMER0_OFF() TCCR0A = 0; TCCR0B = 0 |
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# define TIMER0_CTC_CS256() TCCR0A = _BV(WGM01); TCCR0B = _BV(CS02) |
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# define TIMER0_RESET() TCNT0 = 0 |
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# define TIMER0_COMPARE(t) OCR0A = t |
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# define TIMER0_INT_ENABLE() TIMSK0 = _BV(OCIE0A) |
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# define TIMER0_ISR TIMER0_COMPA_vect |
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#else // ATmega16/32
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# define TIMER0_OFF() TCCR0 = 0 |
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# define TIMER0_CTC_CS256() TCCR0 = _BV(WGM01) | _BV(CS02) |
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# define TIMER0_RESET() TCNT0 = 0 |
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# define TIMER0_COMPARE(t) OCR0 = t |
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# define TIMER0_INT_ENABLE() TIMSK = _BV(OCIE0) |
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# define TIMER0_ISR TIMER0_COMP_vect |
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#endif |
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// buffer which holds the currently shown frame
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unsigned char pixmap[NUMPLANE][NUM_ROWS][LINEBYTES]; |
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// switch to next row
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static void nextrow(uint8_t row) { |
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//reset states of preceding row
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@ -87,6 +99,7 @@ static void nextrow(uint8_t row) { |
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} |
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} |
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// show a row
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static void rowshow(unsigned char row, unsigned char plane) { |
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// depending on the currently drawn plane, display the row for a specific
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@ -96,7 +109,8 @@ static void rowshow(unsigned char row, unsigned char plane) { |
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#else |
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static unsigned char const ocr_table[] = {3, 4, 22}; |
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#endif |
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OCR0 = ocr_table[plane]; |
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TIMER0_COMPARE(ocr_table[plane]); |
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// output data of the current row to the column drivers
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uint8_t tmp, tmp1; |
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@ -135,9 +149,9 @@ static void rowshow(unsigned char row, unsigned char plane) { |
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} |
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// depending on the plane this interrupt triggers at 50 kHz, 31.25 kHz or
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// 12.5 kHz
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ISR(TIMER0_COMP_vect) { |
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// interrupt handler
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ISR(TIMER0_ISR) { |
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static unsigned char plane = 0; |
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static unsigned char row = 0; |
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@ -157,63 +171,27 @@ ISR(TIMER0_COMP_vect) { |
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rowshow(row, plane); |
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} |
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// disables timer, causing the watchdog to reset the MCU
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void timer0_off() { |
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cli(); |
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COLPORT1 = 0; |
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COLPORT2 = 0; |
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ROWPORT = 0; |
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#if defined(__AVR_ATmega164__) || \ |
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defined(__AVR_ATmega164P__) || \ |
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defined(__AVR_ATmega324__) || \ |
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defined(__AVR_ATmega324P__) || \ |
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defined(__AVR_ATmega644__) || \ |
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defined(__AVR_ATmega644P__) || \ |
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defined(__AVR_ATmega1284__) || \ |
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defined(__AVR_ATmega1284P__) |
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TCCR0A = 0x00; |
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TCCR0B = 0x00; |
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#else |
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TCCR0 = 0x00; |
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#endif |
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TIMER0_OFF(); |
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sei(); |
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} |
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// initialize timer which triggers the interrupt
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static void timer0_on() { |
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/* TCCR0: FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00
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CS02 CS01 CS00 |
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0 0 0 stop |
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0 0 1 clk |
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0 1 0 clk/8 |
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0 1 1 clk/64 |
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1 0 0 clk/256 |
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1 0 1 clk/1024 |
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*/ |
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#if defined(__AVR_ATmega164__) || \ |
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defined(__AVR_ATmega164P__) || \ |
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defined(__AVR_ATmega324__) || \ |
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defined(__AVR_ATmega324P__) || \ |
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defined(__AVR_ATmega644__) || \ |
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defined(__AVR_ATmega644P__) || \ |
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defined(__AVR_ATmega1284__) || \ |
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defined(__AVR_ATmega1284P__) |
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TCCR0A = 0x02; // CTC Mode
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TCCR0B = 0x04; // clk/256
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TCNT0 = 0; // reset timer
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OCR0 = 20; // compare with this value
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TIMSK0 = 0x02; // compare match Interrupt on
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#else |
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TCCR0 = 0x0C; // CTC Mode, clk/256
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TCNT0 = 0; // reset timer
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OCR0 = 20; // compare with this value
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TIMSK = 0x02; // compare match Interrupt on
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#endif |
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TIMER0_CTC_CS256(); // CTC mode, prescaling conforms to clk/256
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TIMER0_RESET(); // set counter to 0
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TIMER0_COMPARE(20); // compare with this value first
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TIMER0_INT_ENABLE(); // enable Timer/Counter0 Output Compare Match (A) Int.
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} |
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void borg_hw_init() { |
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// switch column ports to output mode
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COLDDR1 = 0xFF; |
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@ -233,5 +211,5 @@ void borg_hw_init() { |
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// activate watchdog timer
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wdt_reset(); |
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wdt_enable(0x00); // 17ms watchdog
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wdt_enable(WDTO_15MS); // 15ms watchdog
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} |
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